Dr. Sundar lyer, is a Co-Founder, CEO and Member of the Board of Memoir Systems – a memory IP company, productizing Algorithmic Memory that increases embedded memory performance by 10X. Previously, Dr. Iyer was Co-Founder, CTO, and Member of the Board of Nemo Systems – a fabless semiconductor IP company, building 100% hit-rate caching algorithms for scaling the performance of high-speed networking memory systems beyond 100Gb/s. This is largely based on the mathematical work done during his Ph.D. thesis at Stanford University. Dr. Iyer was moreover, a Founding Member and Senior Systems Architect, at SwitchOn Networks – a fabless semiconductor company building co-processor for high-performance data communication systems, founded earlier.
He has also worked as Technical Leader, Co-lead Network Memory Group, Cisco Systems, from October 2005 and December 2008. The group focused on the deployment of the memory caching technology developed at Nemo Systems and new development of memory intelligence and 1/0 serialization technology. Dr. Iyer was a Consultant at Rimo Technologies and Nevis Networks Inc. and a Systems Engineer with PMC-Sierra from 2000 to 2001.
After completing his graduation in Computer Science & Engineering from IIT Bombay in 1998, he went on to undertake an M.S. in Computer Science in the year 2000 (with Distinction in Research) and Ph.D. in Computer Science in 2008, from Stanford University. During his stay as a student on IIT Bombay campus, he served as the General Secretary of H8 (1996-97), General Councilor (1997-98) and was awarded IIT Bombay H8 Roll of Honor in 1998. “There are so many memories of IIT Bombay but I vividly remember going on with less than three hours of sleep for almost 40 days, before the PAF (Performing Arts Festival). Once, I felt asleep and literally kept falling over the stranger sitting on the seat next tome in a BEST bus and was repeatedly berated by him,” he recalled.
Dr lyer is widely acknowledged as a co-inventor of Algorithmic Memory, a technology to solve the ever increasing ‘processor-embedded memory’ performance gap. Algorithmic Memory has been productized and can give up to 10X increase in embedded memory performance, and has been adopted in high-performance networking, cloud infrastructure, data center, SDN, storage and HD-video applications. Previously, Dr. Iyer invented Network Memory, which allowed 100% hit-rate caching algorithms for scaling the performance of high-speed networking memory systems beyond 100Gb/s. The technology reduced the cost of router SRAMs, by over a hundred million dollars annually. It allowed routers to guarantee deterministic memory performance, make them more robust against performance based denial of service attacks and give better deterministic latency guarantees for critical real-time applications on the Internet.
Dr. Iyer has more than 28 publications and 13 US patents to his credit. He has in addition, applied for12 US and foreign patents. Dr. Iyer has delivered several lectures organized in Industry Conferences and Academia, as well as refereed and reviewed several IEEE, ACM and USENIX journals and conferences.
He has also been bestowed with many awards and honours such as the MIT Technology Review (TR35) Young Innovator Award; ACM Best Doctoral Dissertation Award Nominee, Arthur Samuel Best Doctoral Thesis Award at Stanford University, Christofer Stephenson Best Masters Thesis Award at Stanford University. His work on Algorithmic Memory was awarded the Design Vision award in Semiconductor & IP; and was a Best Paper Award Nominee. In 2012, Memoir Systems was been listed among EE-Times ‘Top 10 Memory Design Features for Algorithmic Memory Technology’, the EE-Times ’60 Emerging Silicon Startups for Memoir Systems, the Red Herring ‘Top 100 Award for Memoir Systems’ in May 2012, and featured among the Silicon India ‘Top 5 semiconductor IP companies ‘in 2013.
His areas of interest are not restricted to Improve and Recreational Mathematics. He equally enjoys swimming, running, playing tennis and chess, besides fiction writing and strumming the guitar. He is moreover, a Bronze level II-III dancer in Ballroom Dancing.